View ICS874001AGI-05LF_6978974.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet ics874001agi-05 revision a january 14, 2011 1 ?2011 integrated device technology, inc. pci express? jitter attenuator ics874001i-05 general description the ics874001i-05 is a high perform ance jitter atte nuator designed for use in pci express? systems. in some pci express systems, such as those found in desktop pcs, the pci express clocks are generated from a low bandwidth, high phase noise pll frequency synthesizer. in these systems, a jitte r attenuator may be required to attenuate high frequency random and deterministic jitter components from the pll synthesi zer and from the system board. the ics874001i-05 has a bandwidth of 6mhz with <1db peaking, easily meeting pci express gen2 pll requirements. the ics874001i-05 uses idt?s 3 rd generation femtoclock ? pll technology to achieve the lowest possible phase noise. the device is packaged in a small 20-pin tssop package, making it ideal for use in space constrained applications such as pci express add-in cards. features ? one differential lvds output pair ? one differential clock input ? clk, nclk supports the following input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? input frequency range: 98mhz to 128mhz ? output frequency range: 98mhz to 640mhz ? vco range: 490mhz - 640mhz ? cycle-to-cycle jitter: 50ps (maximum) ? full 3.3v operating supply ? pci express (2.5gb/s) and gen 2 (5 gb/s) jitter compliant ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 f_sel0 v dda f_sel1 nc mr nc nc nc pll_sel v dd nc v ddo q nq nc nc gnd ncl k clk oe pin assignment phase detector vco 490 - 640mhz output divider 0 0 5 0 1 4 1 0 2 (default) 1 1 1 5 0 1 internal feedback q nq pll_sel clk nclk mr f_sel[1:0] oe pulldown pullup/pulldown pullup pullup pullup pulldown 2 ics874001i-05 20-lead tssop 6.5mm x 4.4mm x 0.925mm package body g package top view block diagram
ics874001agi-05 revision a january 14, 2011 2 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 pll_sel input pullup pll select pin. when low, bypasses t he pll. when high selects the pll. lvcmos/lvttl interface levels. see table 3b. 2, 3, 4, 6, 15, 16, 20 nc unused no connect. 5 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true output q to go low a nd the inverted output nq to go high. when logic low, the internal dividers and the outputs are enabled. lvcmos/lvttl interface levels. 7 f_sel1 input pullup frequency select pin. lvcm os/lvttl interface levels. see table 3c. 8v dda power analog supply pin. 9 f_sel0 input pulldown frequency select pin. lv cmos/lvttl interface levels. see table 3c. 10 v dd power core supply pin. 11 oe input pullup output enable. when high, outputs are enabled. when low, forces outputs to a high-impedance state. lvcmos/lvttl interface levels. see table 3a. 12 clk input pulldown non-inverting differential clock input. 13 nclk input pullup inverting differential clock input. 14 gnd power power supply ground. 17, 18 nq, q output differential output pair. lvds interface levels. 19 v ddo power output supply pin. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics874001agi-05 revision a january 14, 2011 3 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator function tables table 3a. output enable function table table 3b. pll_sel control table table 3c. f_selx function table inputs outputs oe q, nq 0 high-impedance 1 (default) enabled inputs function pll_sel 0 bypass 1 vco (default) inputs output frequency (mhz) f_sel1 f_sel0 output divider 0 0 5 98 - 128 0 1 4 122.5 - 160 1 0 2 245 - 320 (default) 1 1 1 490 - 640
ics874001agi-05 revision a january 14, 2011 4 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at th ese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 0.3v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 0.3v, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ja 86.7c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.0 3.3 3.6 v v dda analog supply voltage v dd ? 0.13 3.3 v dd v v ddo output supply voltage 3.0 3.3 3.6 v i dd power supply current 75 ma i dda analog supply current 13 ma i ddo output supply current 25 ma symbol parameter test conditi ons minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current pll_sel, f_sel1, oe v dd = v in = 3.6v 5 a f_sel0, mr v dd = v in = 3.6v 150 a i il input low current pll_sel, f_sel1, oe v dd = 3.6v, v in = 0v -150 a f_sel0, mr v dd = 3.6v, v in = 0v -5 a
ics874001agi-05 revision a january 14, 2011 5 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator table 4c. differential dc characteristics, v dd = v ddo = 3.3v 0.3v, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4d. lvds dc characteristics, v dd = v ddo = 3.3v 0.3v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current clk v dd = v in = 3.6v 150 a nclk v dd = v in = 3.6v 5 a i il input low current clk v dd = 3.6v, v in = 0v -5 a nclk v dd = 3.6v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 275 375 485 mv ? v od v od magnitude change 50 mv v os offset voltage 1.20 1.35 1.50 v ? v os v os magnitude change 50 mv
ics874001agi-05 revision a january 14, 2011 6 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator ac electrical characteristics table 5. ac characteristics, v dd = v ddo = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device w ill meet specifications after th ermal equilibrium has been reached under these conditions. note 1: this parameter is defined in accordance with jedec standard 65. note 2: peak-to-peak jitter after applyi ng system transfer function for the common clock architecture. maximum limit for pci ex press gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. note 3: rms jitter after applying the tw o evaluation bands to the two transfer func tions defined in the common clock architectu re and reporting the worst case results for each evaluation band. ma ximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). note 4: guaranteed only when input clock source is pci express and pci express gen 2 compliant. symbol parameter test conditio ns minimum typical maximum units f out output frequency 98 640 mhz t jit(cc) cycle-to-cycle jitter; note 1 50 ps t j (pcie gen 1) phase jitter peak-to-peak; note 2, 4 100mhz output, evaluation band: 0hz - nyquist (clock frequency/2) 16.14 ps 125mhz output, evaluation band: 0hz - nyquist (clock frequency/2) 15.64 ps 250mhz output, evaluation band: 0hz - nyquist (clock frequency/2) 13.16 ps 500mhz, (1.2mhz ?21.9mhz), evaluation band: 0hz - nyquist (clock frequency/2) 12.17 ps t refclk_hf_rms (pcie gen 2) phase jitter rms; note 3, 4 100mhz output, high band: 1.5mhz - nyquist (clock frequency/2) 1.4 ps 125mhz output, high band: 1.5mhz - nyquist (clock frequency/2) 1.39 ps 250mhz output, high band: 1.5mhz - nyquist (clock frequency/2) 1.18 ps 500mhz output, high band: 1.5mhz - nyquist (clock frequency/2) 1.11 ps t refclk_lf_rms (pcie gen 2) phase jitter rms; note 3, 4 100mhz output, low band: 10khz - 1.5mhz 0.33 ps 125mhz output, low band: 10khz - 1.5mhz 0.22 ps 250mhz output, low band: 10khz - 1.5mhz 0.22 ps 500mhz output, low band: 10khz - 1.5mhz 0.22 ps t r / t f output rise/fall time 20% to 80% 200 600 ps odc output duty cycle f_sel[10] 11 48 52 % f_sel[10] = 11 42 58 %
ics874001agi-05 revision a january 14, 2011 7 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator parameter measureme nt information 3.3v lvds output load ac test circuit output duty cycle/pulse width/period output rise/fall time differential input level cycle-to-cycle jitter offset voltage setup scope qx nqx 3.3v0.3v power supply +? float gnd lvds v dda v dd, v ddo t pw t period t pw t period odc = x 100% q nq 20% 80% 80% 20% t r t f v od q nq v dd nclk clk gnd v cmr cross points v pp ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles q nq out out lvds dc input ? ? ? v os / ? v os v dd
ics874001agi-05 revision a january 14, 2011 8 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator parameter measurement in formation, continued differential output voltage setup applications information recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. ? ? ? 100 out out lvds dc input v od / v od v dd
ics874001agi-05 revision a january 14, 2011 9 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
ics874001agi-05 revision a january 14, 2011 10 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are exam ples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver figure 2f. clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 *r4 33 clk nclk 3.3v 3.3v zo = 50 zo = 50 differential input r1 50 r2 50 *optional ? r3 and r4 can be 0 clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50 clk nclk differential input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics874001agi-05 revision a january 14, 2011 11 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator lvds driver termination a general lvds interface is shown in figure 3. standard termination for lvds type output stru cture requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 3 can be used with either type of output structure. if using a non-standard termination, it is recommended to contact idt and conf irm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. figure 3. typical lvds driver termination 100 ? + 100 differential transmission line lvds driver lvds receiver
ics874001agi-05 revision a january 14, 2011 12 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator pci express a pplication note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase in terpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiv er is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the enti re spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s () h3 s () h1 s () h2 s () ? [] = ys () xs () h3 s () h1 s () h2 s () ? [] =
ics874001agi-05 revision a january 14, 2011 13 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator schematic layout figure 4 shows an example of ics8740 01i-05 application schematic. in this example, the device is operated at v dd = v dda = v ddo = 3.3v. the input is driven by a 3.3v lvpecl driver. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the ics74001i-05 provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter componen ts be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed fo r wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. figure 4. ics874001i-05 schematic layout set logic input to '1' to logic input pins oe vdd c9 10uf mr r4 50 c2 10u c6 0.1uf vdd c7 10uf + - logic control input examples nq + - rd1 not install zo = 50 ohm vdd to logic input pins ru2 not install c4 0.01u r2 100 u1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 nc nc nc mr nc f_sel1 vdda f_sel0 vdd oe clk nclk gnd nc nc nq q vddo nc pll_sel r3 50 c3 0.1u vddo lvpecl driv er set logic input to '0' f_sel0 zo_dif f = 100 ohm pll_sel nclk alternate lvds termination nclk vdd nq blm18bb221sn2 ferrite bead 1 2 vdda r6 50 rd2 1k q clk r1 10 ru1 1k c1 0.1u zo = 50 ohm q c8 0.1uf 3.3v f_sel1 blm18bb221sn1 ferrite bead 1 2 3.3v clk zo_dif f = 100 ohm gnd lvds termination r5 50 r7 50 c5 0.1uf vdd vddo
ics874001agi-05 revision a january 14, 2011 14 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator power considerations this section provides information on power dissipati on and junction temperatur e for theics874001i-05. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics874001i-05 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 0.3v = 3.6v, which gives worst case results. power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.6v * (75ma + 13ma) = 316.8mw power (outputs) max = v ddo_max * i ddo_max = 3.6v * 25ma = 90mw total power_ max = 316.8mw + 90mw = 406.8mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 86.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.407w * 86.7c/w = 120.3c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 20 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 86.7c/w 82.4c/w 80.2c/w
ics874001agi-05 revision a january 14, 2011 15 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator reliability information table 7. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ics874001i-05 is: 1,608 package outline and package dimensions package outline - g suffix for 20 lead tssop table 8 package dimensions reference document: jedec publication 95, mo-153 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 86.7c/w 82.4c/w 80.2c/w all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics874001agi-05 revision a january 14, 2011 16 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 874001agi-05lf ics4001ai05l ?le ad-free? 20 lead tssop tube -40 c to 85 c 874001agi-05lft ics4001ai05l ?lead-fr ee? 20 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics874001agi-05 revision a january 14, 2011 17 ?2011 integrated device technology, inc. ics74001i-05 data sheet pci express? jitter attenuator revision history sheet rev table page description of change date a t5 6 9 11 12 13 updated hcsl notes. deleted power supply filtering techniques application note (see schematic application). updated wiring the differential input to accept single-ended levels application note. updated lvds driver termination application note. update pci express application note. updated schematic layout application note and diagram. converted datasheet format. 1/14/11
ics74001i-05 data sheet pci express? jitter attenuator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informati on contained herein is provided without re presentation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantabilit y, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ris k, absent an express, written agreement by idt. integrated device technology, idt and the idt l ogo are registered trademarks of idt. ot her trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

▲Up To Search▲

Price & Availability of ICS874001AGI-05LF

	To Download ICS874001AGI-05LF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .